Quad Flat No-Lead (QFN) semiconductor packages have achieved wide popularity in recent years because of their smaller package size. QFN packages typically come in a variety of sizes and are often classified according to their size. For example, a QFN package may be referred to as a “4×4” QFN package or a “6×6” QFN package, meaning that the QFN package includes width dimensions of 4 mm by 4 mm, or 6 mm by 6 mm, respectively. Generally, QFN packages are more than 20% larger in area than the semiconductor chip contained with the QFN package, and therefore, are not classified as chip-scale packages.
FIG. 1 is a diagram illustrating a bottom view of a typical QFN package 100. As illustrated, QFN package 100 includes a plurality of leads 105 and a flag 120 exposed on a mounting side 107 formed from a mold material 140 of QFN package 100, wherein leads 105 are typically embedded within mold material 140 so as to be less prone to bending and configured to couple QFN 100 to a printed circuit board (PCB, not shown). Typical leads 105 include a generally rectangular shape such that leads 105 are substantially co-planar with mounting side 107. Moreover, the number of leads 105 included on any particular QFN package 100 varies with the size of QFN package 100. For example, one 4×4 QFN package (i.e., QFN package 100) may include 16 leads (e.g., 4 leads on each side). In addition, flag 120 is typically square-shaped and is utilized for electrical and/or thermal connection between the PCB and a semiconductor chip (discussed below) included within QFN package 100.
FIG. 2 is a diagram illustrating a cross-section view of QFN package 100, wherein QFN package 100 includes a semiconductor chip 110 attached to a flag 120 (or chip pad). Flag 120 is typically formed from a conductive material (e.g., a metal) and includes a mold lock 125 utilized to attach flag 120 to a mold material 140.
Semiconductor chip 110 includes an inactive surface 112, which is utilized to attach semiconductor chip to flag 120 via an adhesive material (e.g., epoxy, tape, solder, or the like, not shown). Furthermore, semiconductor chip 110 includes an active surface 114 having one or more bond pads 118 located at a perimeter 116 of active surface 114, wherein bond pad(s) 118 enable semiconductor chip 120 to be coupled to one or more of leads 105 via one or more wire bonds (discussed below). Semiconductor chip 110 may be formed of, for example, silicon, silicon dioxide, germanium, gallium arsenide, and/or similar material(s), and may be, for example, a complementary metal-oxide semiconductor (CMOS) chip, a micro-electro-mechanical (MEMS) chip, or similar semiconductor chip.
In addition, QFN package 100 includes a plurality of wire bonds 130 for attaching leads 105 to semiconductor chip 110. Wire bonds 130 are typically formed of a conductive material such as, for example, copper, gold, silver, platinum, or similar conductive material. Moreover, wire bonds 130 are usually attached proximate to perimeter 116 of active surface 114 such that each wire bond 130 includes a portion 132 that extends “upwardly” from semiconductor chip 110, a “looped” portion 134, and an inflection point 136 followed with wire that extends “downwardly” with further curvature to wire bond parallel to the surface of lead 105. This wire curvature provides sufficient ball bond strength to both bond pad 118 and to lead 105 and prevents wire bond 130 from coming into contact with semiconductor chip 110 at undesirable points.
Once semiconductor chip 110 is attached to flag 120 and one or more leads 105 via wire bond(s) 130, these components are molded together utilizing mold material 140, wherein mold material 140 forms mounting side 107, a top side 108 oriented substantially opposite mounting side 107, and a plurality of lateral sides 109. Mold material 140 is typically a plastic or similar non-conductive material, and is utilized to protect semiconductor chip 110, flag 120, and wire bonds 130.
As discussed above, because it is desirable that wire bond(s) 130 be attached to lead(s) 105 and semiconductor 110 such that wire bond(s) 130 do not contact semiconductor 110 at undesirable points, a certain minimum width “W” is needed on each side of semiconductor chip 110 and/or a certain height “H” is needed above semiconductor chip 110 to ensure there is sufficient room for wire bond(s) 130 to clear semiconductor 110, but not protrude through top side 108 of mold material 140. Semiconductor chip 110 is typically not perfectly square; nevertheless, the two “Z” widths of semiconductor chip 110 are smaller than the two “Z′” width dimensions of flag 120. Moreover, each lead 105 is separated from flag 120 by a distance “D.” The width “W,” flag width “Z′”, separation spacing “D,” and/or height “H” results in QFN package 100 being larger than it otherwise could be.
Various materials having different coefficients of expansion (CTE) may be utilized to construct QFN package 100. When QFN package 100 includes an organic mold material 140 and a metallic flag 120 structure having a semiconductor chip “sandwiched” in-between them (discussed below), QFN package 100 will generally create bending forces similar to bi-metallic strips during subsequent exposure to heating and cooling conditions. As a result, QFN package 100 will typically contain inherent residual stress that can warp or bend QFN package 100, which can lead to package failure (e.g., delamination between mold material 140 and leads 105).
To reduce the amount of residual stress, flag 120 and/or leads 105 include mold locks 125 to increase adhesion between mold material 140 and metal flag 120 and/or between mold material 140 and leads 105. In other words, mold locks 125 help to minimize package delamination caused by residual bending forces.